The present invention generally relates to the design of buses used to carry power and/or ground in semiconductor design or manufacturing, and more specifically relates to a multi-layered staggered power bus layout design.
As semiconductors become smaller, the input/output area is impacted. Although it is often desired to design a smaller input/output area, in order to maintain current carrying capabilities, the strips forming the power and ground buses must meet a minimum width requirement. The number of strips need for each power and ground bus is determined by the maximum metal width. A metal utilization upper limit determines how compact the buses can be placed within the layout. These limitations present two difficulties for the input/output bus layout. The metal utilization limit determines the extent to which the input/output can be reduced while the maximum metal width determines the current each strip of metal can carry.
Current methods used to resolve the metal utilization problem include using a single layer of metal or using multiple layers of metal. If only one layer of metal is used, generlly the input/output occupies a large area on the silicon. When multiple layers of metal are used, identical geometries are generally used on adjacent metal layers so that the input/output area can be reduced due to the fact that the power/ground current are carried by multiple layers of metal.
Problems occur when using these methods to resolve the maximum metal width and metal utilization problems. For example, current bottle necks occur in traditional wire bond, pad on I/O wire bond, and flip chip bond, therefore, electronic migration becomes an issue. In addition, tools need to be developed to account for different bonding schemes and to ensure each strip of the metal bus carries a certain amount of current. Currently, these tools are not available.